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Altera_Forum
Honored Contributor
14 years agoJust an update, I seem to have fixed this issue. In case anyone has similar symptoms in the future:
My original design had two PLLs, one producing the 40 MHz clock for the Nios system and one producing a 400 MHz for the LFSR. When I used a single PLL with two clocks, at 40 and 400 MHz, the issue disappeared.