nios in stratix dsp board

I have managed to get the IDT SSRAM working on that board. I have a class.ptf and a VHDL or Verilog file that I can send you to get it up and running.

Note that a PLL is needed to generate two separate clocks - One feeding the Nios II processor, the other is 180 degrees out of phase with the processor clock and feeds the SSRAM clocks (this helps to centre align clock with data).

As for the Flash device. I haven't tried that, but I suspect you could use the CFI compliant device in SOPC builder and modify it to meet your Flash memory needs - such as number of address lines, and timing, etc.

Send me an email and I will send you the ssram files. That should get you started. (I would post them here, but not too sure how)

-Terry