NIOS II Power and Heat management

Hi,

To answer the first quesiton,

- Targeted Device: Stratix / Stratix II

-# of NIOS II Cores: varies

- The speed of the circuit: also varies

- unuse I/O: Tristate

- Device Utilization: Depends on the device (still in conceptual stage of designing)

As for possible power saving design choices, I have explored:

- Disabling the clock (or Vcc-ing it) of NIOS II cores.

This reduces power consumption and heat when done while the design is running.

If this is done directly in the design, Quartus II will not include the disabled cores in the

compile.

- Disabling the output of NIOS II cores

Has the same effect as diabling the output.

- Bringing down the clock's frequency

The design's frequency has a proportional relationship with the power consumption of

the design. In a 12 Core design, when the frequency was cut from 80MHz to 40MHz the

temp went down by about 15 degrees celcius.

Still trying to find a NIOS II equivalent to 'low-power' or 'standby'.

I hope this extra info helps find a solution. thanks.