NIOS II Power and Heat management

Hi all,

this is a question that also interests us a lot... not from a point of view of producing final products, but (at the moment) for basic research.

In particular, we have connections with our local University, and there is a research group researching on power-related issues from a perspective of the OS (how can be the OS/firmware designed to use the hardware in the best way to save as much energy as possible?)... and they are interested in having multiprocessor designs that can be tuned in terms of power consumption.

From our point of view, it would be interesting to know which are the possible design choices available on Nios II FPGAs that can be put in place to save power, like:

- slowing down frequency

- stop processors from executing

- stop entire parts of a design (processor+peripherals?)

bye

PJ