NIOS : IOWR works fine but writing through a pointer not

IOWR() uses the 'stio' instruction in order to bypass the data cache.

If you aren't using the mmu (likely unless you are running something like linux) then you can also bypass the data cache by setting bit31 of the address.

If all your data memory is internal to the fpga (ie not SRAM/SDRAM/DDR) then you might as well connect it as 'tightly coupled data memory' and completely remove the data cache.

An avalon slave can (IIRC) latch the data for writes in one clock - as fast as the nios can ever write data, so there is no point supporting burst write transfers.

Avalon reads (by the nios) do have at least one wait state - as well as the two clock delay before the data can be used. In practise this is likely to be less than the cost of setting up any other form of transfer.

If you want to process large blocks of data, an an avalon master interface to your logic block.