Multi NIOS2 system Custom instruction opcode reuse problem in QSys

Either way should work assuming this is still an issue with the latest tools (not sure haven't checked myself).

If you want a shared address space then I would put a CPU into it's own subsystem with it's own set of custom instructions to avoid this issue. For shared peripherals/memories just put a pipeline bridge into each CPU subsystem and export the master of the bridge. Then at the top level (or whatever heirarchy level the shared components live) connect those exported bridge masters to all the slaves you want both CPUs to see. Just make sure you expose enough address bits for each of those pipeline bridges to span all the slave ports you want each CPU to have access to.