Multi NIOS2 system Custom instruction opcode reuse problem in QSys

Just to make sure I've got this right, if they aren't connected in the "Connections" column in QSys, they aren't connected, right?

The custom instruction master of each CPU is only connected to the custom instruction associated with the CPU. "cpu"'s custom instruction master is only connected to "CRC_0"'s custom instruction slave. "cpu_0"'s custom instruction master is only connected to "CRC_1"'s custom instruction slave.

Here's step by step everything I did in QSys to get the error:

Started from a new system that only has a Clock Source.

Add a NIOSII/f (named nios2_qsys_0)

Set Reset vector memory to jtag_debug_module

Set Exception vector memory to jtag_debug_module

Instruction cache is set to 512 Bytes

Data Cache is set to None

clk and reset_n are hooked up to the Clock Source.

Add a CRC (named CRC_0)

Hook custom instruction master to custom instruction slave.

Add a second NIOSII/f (named nios2_qsys_1)

Set Reset vector memory to jtag_debug_module

Set Exception vector memory to jtag_debug_module

Instruction cache is set to 512 Bytes

Data Cache is set to None

clk and reset_n are hooked up to the Clock Source.

Add a CRC (named CRC_1)

Hook custom instruction master of the second NIOSII/F to custom instruction slave of the second CRC.

I confirm that both custom instruction use the OpCode range 0-7.

I did NOT make any connection between the first CPU master and the second custom instruction slave or a connection between the second cpu master and the first custom instruction slave.

Save System and Generate.

The same error appears:

Info: nios2_qsys_0: ERROR:

Info: nios2_qsys_0: msb of '2' is less than lsb of '3' for custom instruction 'crc_0' (addr_base='0', addr_width='3', master_n_field_decode_sz='3'

Error: nios2_qsys_0: Failed to generate module niosii_3c25_system_3_nios2_qsys_0

If it matters, the CRC Custom Instruction comes from the "Nios II Custom Instruction Design Example" on the Altera website.