making an IP for DMA transfers

In the process of doing something similar but need to cross from transceiver derived clock to system clock and 16bit data to 32bit storage.

For now trying to avoid much user logic.

Transceiver --> (16b)FIFO(32b)-->Qsys-->(ST) FIFO (MM) --> (MM) DMA (MM) --> (MM) DDR3 SDRAM

The megawizard DCFIFO does the clock and bit cross, the Qsys on chip FIFO ST port provides the pin access, and the DMA (with its own FIFO) pumps data to DDR3.

So that's 3 FIFOs.

Possible alternative would be to create a Qsys new component FIFO to combine the function of the OnChip and the Wizard FIFOs. Probably easy but would like to know how.