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Altera_Forum's avatar
Altera_Forum
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20 years ago

linker script and dual port memories

Hi everybody,

that's probably a simple question, basically I cannot find where to look at:

I have a design with a CPU that has an instruction master and a data master.

First case

------------

there is a dual ported onchip ROM memory, with two slaves s1 and s2.

- s1 is connected to the CPU instruction master,

- s2 is connected to the CPU data master.

- system library properties specifies .text should go into s1

The automatically generated linker script has this relevant informations:

on the MEMORY part,

onchip_rom_cpu_2_s1 : ORIGIN = 0x00800020, LENGTH = 65504

onchip_rom_cpu_2_s2 : ORIGIN = 0x00800020, LENGTH = 65504

on the SECTIONS part, there is:

.exceptions :

{

....

} > onchip_rom_cpu_2_s2

.text :

{

....

} > onchip_rom_cpu_2_s1 =0x3a880100 /* NOP on Nios2 (big endian) */

Question:

- why the exceptions section is located onchip_rom_cpu_2_s2 --> is it a data port!

Second case

---------------

there is a dual ported onchip ROM memory M1, with two slaves M1_s1 and M1_s2.

there is another onchip rom memory M2

- M1_s1 and M2 are connected to the CPU instruction master,

- M1_s2 is connected to the CPU data master.

- system library properties specifies .text should go into M1_s1

M1 appears before (or after, it is the same) M2 in SOPCBuilder

in this case, exceptions goes to M2, .text goes to M1_s1

Questions:

- is there a way from the system library dialog box to say that .exceptions should go in a particular section?

Thanks again for all the support,

Paolo

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Ok, just a reply to myself:

    - I guess the .exceptions section goes to the same section that is specified in sopcbuilder in the nios2 tab becaus ethe exceptions section contains the interrupt code that have to stay at the cpu exceptions place. --> so the question in the second case was ok.

    - however, the strange thing is that in the first case in SOPCBuilder I set the exception address to go in s1, but the linker script says s2 (that is the data port)!!! --> so the question in the first case still remains...

    PJ
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Again a reply to myself.

    After trying a few times on different PCs to reproduce the strange behavior, I maybe found a way to reproduce it (I hope that this sequence will work on your machines):

    - make a copy of a "fast example"

    - open quartus, then sopcbuilder

    - add a dual port onchip ram (with slaves s1 and s2)

    - add a tightly coupled data port to the cpu

    - connect s1 only to the instruction master

    - connect s2 only to the tightly coupled data master of the cpu

    - in the "More CPU settings" tab put the reset and exception address in s1

    - exit sopcbuilder

    - open Nios II IDE

    - create a systemlibrary based on the ptf just generated by sopcbuilder

    - open the system library property

    - set the .text to s1

    - build the system library

    look at generated.x. On my machine, it contains the following:

    <div class='quotetop'>QUOTE </div>

    --- Quote Start ---

    .exceptions :

    {

    ...

    } > onchip_memory_0_s2

    ...

    .text :

    {

    .....

    } > onchip_memory_0_s1 =0x3a880100 /* NOP on Nios2 (big endian) */[/b]

    --- Quote End ---

    I think that is maybe wrong, because it is putting .exceptions in s2 that is the space of the data master that also has the SAME address of s1... the result at the end is that if you compile a simple application, the .exceptions data section will conflict with the .text data section...

    bye

    PJ