Issue with the application layer from NIOS II IDE while accessing a custom instructio

Hello,

Sorry, it had been my fault in the verilog and the fault was with respect to the timing.

Earlier, I had been trying to do the ADD operation and read the result output port in the same clock cycle which was making the module confused

and I guess the dataa port had been getting unknown value (like 2047) because of that timing issue. I really appreciate for BadOmen who made me

to look into the custom instruction timing diagram once again (I am just a beginner).

See what I did now is having separate 'write' and 'read' instructions and added the lines of code in verilog module custom_Component.v

if(write && chipselect) begin

cin = 0;

{cout, output_value} = writedataa + writedatab + cin;

end

else if((read == 1) && (chipselect == 1))

begin

readdata <= output_value;

end

so that before reading a result port, there will be a write latency.

I tried to access from the application code (in NIOS II IDE) like this:

/* Write Sum */ dataa = 0XFFFFFFFF;

datab = 0XFFFFFFFF;

sumOutput = ALT_CI_CUSTOM_ADD_INST(1,dataa,datab);

printf("\nThe result line value is %lu",sumOutput); // Expect some unknown value to print

/* Read Sum */

sumOutput = ALT_CI_CUSTOM_ADD_INST(4,dataa,datab); // Expect the earlier SUM value to print

printf("\nThe SUM of %lu and %lu is %lu",dataa,datab,sumOutput);

And the sumOutput variable printed an expected value!.

I appreciate the effort taken by forum admins to sort this out.

Thank You,

Akhil