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The interrupt entry/exit code paths and any SDRAM accesses could easily dominate that workload.
The PIO reads themselves are likely to take 3 clocks, with a 2 clock stall if the result is needed by the next instruction.
A 120MHz cpu gives you 20*120 = 2400 clocks between each of your PIO interrupts.
So you should easily be able to write interrupt entry/exit code and do the required transfers within that period.
The problem is likely to be code that disables your interrupt - especially other interrupts (unless you have a multi-level interrupt controller with the priorites set 'correctly'). In particular I suspect that the JTAG debug and UART will have longer ISRs.
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Maybe i could explain my problem more detailedly. I did a AD-Collection and ethernet transfer(with DP83848 and TSE MAC) module. I test the module with 16-bit counter. I read the AD data by PIOs every time the external synchronizing signal reaches a falling edge. Now everything seems OK but some data loses but not packet loses.I suspect the time for the interrupt to response isn't long enough, although the response time is 20us.
Ps: I've already set the synchronizing signal interrupt priority to No.1.
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