Honored Contributor
Honored ContributorThe interrupt entry/exit code paths and any SDRAM accesses could easily dominate that workload.
The PIO reads themselves are likely to take 3 clocks, with a 2 clock stall if the result is needed by the next instruction. A 120MHz cpu gives you 20*120 = 2400 clocks between each of your PIO interrupts. So you should easily be able to write interrupt entry/exit code and do the required transfers within that period. The problem is likely to be code that disables your interrupt - especially other interrupts (unless you have a multi-level interrupt controller with the priorites set 'correctly'). In particular I suspect that the JTAG debug and UART will have longer ISRs.
