Honored Contributor
Honored Contributor1)
If you want really hard real time, you can do this by using a counter with a pll on the clock. All in pure FPGA logic : no random external events (except upset events caused by radiations of course), very ultra deterministic, very easy to make... ^^^ Very optimized !! :-) ultra low resources, quite robust, MTBF near MTBFof FPGA, ultra simple to design.... 2) You can configure timer to produce interruptions at a fixed period : no need to stop and start by the software. Take the features of FPGA : programmable gate array. Else a computer (PC, MAC, rasberry...) would be sufficent ;-) 3) optimisations of uc/OS : tedious work and may not be sufficient. (Mistake) --- Quote Start --- My board starts for a long time --- Quote End --- BUT your operating procedure show us that you measure the boot time + duration until first interruption. (Am I Right ?) You mismatch yourself OR I misunderstood/forgot something. I am very confused HERE NOW.
