Internal port timing detail in simulation

Could be a fundamental question.

I was trying to study accurate timing of internal port. (not stand alone register)

I used to do this by adding OUTPINs in design, since doing this will introduce path delay into timing simulation, which is not desirable.

In Node Finder of wave editor, options of filter:

registers: pre-synthesis

registers: post-fitting

design entry (all names)

post compilation

might be right for use, but I failed in getting any effective output from my design.

Generally my top level design is in schematic.

Need timing of ports, should I register them? or there are other options?

Please help,

Thx