Interconnections and interrupts between nios processors

Are your Nios cpu on the same fpga - I assume so but someone mentioned SPI...

I'm not sure why you mentioned a pipelined bridge either. For speed you can dual port an internal memory block as 'tightly coupled data memory' to both cpu. Or maybe make it an Avalon slave to one and tightly coupled to the other.

If you need interrupts a small slave device that asserts an IRQ when 'set' will do. It can be worth having two locations and doing write-to-set and write-to-clear. Also worth supporting multiple bits and or'ing them onto the actual hw interrupt, maybe an enable mask as well! Oh - and you might as well hook up the nios soft reset lines to one of the bits....

Depending on the 'OS' (or lack of it!) you are using, interrupts may not be needed. If your code has an idle loop (probably calling a few functions) just check for 'work do to' in that loop. Saves the cost of the register saves in the ISR, and all the interrupt masking and deferring work to a non-interrupt context that is usually needed with ISRs.