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Altera_Forum's avatar
Altera_Forum
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14 years ago

Input file is too large to fit (Nios Programmer)

Wondered if anybody can guide me in the right direction with an issue I am having with the nios flash programmer.

I am using a ArriaIIgx 95K logic being configured by an EPCS64 device. I store my FPGA config data and software in the EPCS. I use the default boot loader to copy the software out of epcs and into 94KB of onchip ram. My reset vector is set for the EPCS flash controller

In the nios flash programmer, I take my .sof and .elf and use the nios GUI programmer to program it in. I get an error stating the " Input is too large to fit".

Here is what I have tried

1) The application code can be put inside the on_chip_ram as an initialisation file and then built. It can be downloaded as a .sof or.jic and the design and the software run. This is fine.

2) I have created the hello world small design and built it. It still complains about the size of the file.

3) Using the flash programmer, just trying to download the .sof (containing just the FPGA image (no software)) says that the input file is too large. The .sof can be downloaded using the quartus programmer and works.

4) Tried following other posts from the nios forum. Converting the .sof to a flash file and then converting .flash to a bin file. Next take the elf to bin and then concatenating the two bins in to one. Then convert bin to .hex. Use .hex alone in a .jic. When converting in to a .jic it fails complaining that the file is to big to fit in the EPCS64. It also fails on the EPCS128. The .hex file that is used for .jic conversion is 46MB.

5) Once the .sof that contains the FPGA image is inside (using the quartus programmer), I can use the hardware debugger to get the code inside the nios and it runs fine.

6) When I tried to put the .sof and .elf in using the flash programmer the GUI uses the following commands. As far as I can see the options look correct.

sof2flash --input="C:/FPGACode/Hello/top.sof" --output="C:/FPGACode/Hello/software/Hi_bsp/flash/top_epcs_flash_controller_0.flash" --epcs –verbose

elf2flash --input="C:/FPGACode/Hello/software/Hi/Hi.elf" --output="C:/FPGACode/Hello/software/Hi_bsp/flash/Hi_epcs_flash_controller_0.flash" --epcs --after="C:/FPGACode/Hello/software/Hi_bsp/flash/top_epcs_flash_controller_0.flash" --verbose

nios2-flash-programmer "C:/FPGACode/Hello/software/Hi_bsp/flash/top_epcs_flash_controller_0.flash" --base=0x41800 --epcs --sidp=0x424D0 --id=0x0 --timestamp=1331039095 --device=1 --instance=0 '--cable=ByteBlasterII on localhost [LPT1]' --program –verbose

nios2-flash-programmer

"C:/FPGACode/Hello/software/Hi_bsp/flash/Hi_epcs_flash_controller_0.flash" --base=0x41800 --epcs --sidp=0x424D0 --id=0x0 --timestamp=1331039095 --device=1 --instance=0 '--cable=ByteBlasterII on localhost [LPT1]' --program –verbose

I have also attached a picture of the error

I would very much appreciate any help anyone can give me

C

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    pancake,

    Thanks for your reply.

    Yes I have tried the -compress flag (although its not shown in this example).

    It didn't make any difference.

    C
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    i would try File > Convert Programming Files to create a .jic file containing the compressed .sof and .hex

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Pancake,

    I am struggling to do the .sof and .hex together in the same .jic. It tells me the hex and sof overlap

    I produced the .hex in a few ways. I used the mem_int make file in nios IDE to produce the initialisation .hex file that you would normally use inside the onchip ram. I also used the elf2hex command.

    The command I used was

    elf2hex --input="myfile.elf" --width=32 --base=0x20000 --end=0x367ff

    :confused:

    C
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    another clue in this is when I do the nios programmer elf and sof conversion to make the flash file. It comes out at 47MB. Using the 'nios2-elf-size' command on the flash file it comes out at exactly the size of an EPCS128 device. This is even with just a processor and a hello world program in it.

    I state in the 'devices section' in quartus that my conf device will be a EPCS64
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    i remember having to play around to get the .hex to immediately follow the .sof. i will see if i can play around with it again

    the key is checking the .map file after generation to see that the .hex is at the address immediately after the .sof
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks pancake.

    I have managed to create a .jic with the config data and the hex data

    the map file looks like this

    BLOCK START ADDRESS END ADDRESS

    Page_0 0x00000000 0x0026851A

    App2.hex 0x0026851B 0x002AED1A

    The key to making it do this this was creating a hex file from the .elf and then correcting for a problem in quartus detailed here

    http://www.altera.com/support/kdb/solutions/rd09282011_907.html

    Next, in the convert programming files add the flash loader and the .sof. Next add the .hex data with 'relative addressing' switched on but no address set.

    This file fits into a EPCS64.

    Problem is that the software doesn't run. The design runs though. I am not sure how the epcs flash loader knows where to find the code. Does it just assume it is going to be directly after the file? Also if we are using this method, does the .hex have to be created differently from the elf2hex format?

    C
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    yes, i think the .sof has a header that says its length. the default bootloader jumps to the address immediately following the .sof and starts reading

    elf2hex should work. unfortunately it's been a long while since i've done this so i'd have to find a board with EPCS to take a further look
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Had to raise an SR to get an answer on this.

    This is a bug in the tool chain and was fixed in version 11.1 of Nios tools

    C