Forum Discussion
Altera_Forum
Honored Contributor
16 years agoAs already said in the other thread, I don't suppose it's a good idea to access anything (in fact especially memory) from both CPUs via the same Avalon bus.
Moreover I don't think it's a good idea to (in Linux) access anything from userland software using the "0x80000000 + hardware_address". There are decent (portable) means provided to do this (e.g. using "uio" from user land or better doing a decent Kernel driver) and using the correct (portable) macros provided to avoid caching. But of course for testing purpose you can happily ignore these suggestions. You do know that (only with a non-MMU-NIOS2-system) setting bit 31 means "don't cache" ?!?!?!? Thus in your test you might try to use the "0x80000000 + hardware_address" notation with your second CPU as well, if same is a NIOS2 without MMU and with data-Cache. -Michael