How to increase DMA fifo depth?

Thanks Koma,

I should update this thread with the latest. Raising the fifo depth helps a bit, but there is a problem in that the dma reads do not heed the FIFO_FULL flag and so anytime your Avalon bus gets busy during a dma it can corrupt the data.

I have submitted this as a bug to Altera and hope it will be fixed very soon.

I looked through the dma HDL to see if it would be simple to qualify the reads with !FIFO_FULL, but I'm afraid my HDL skills are nil.

I think Altera must have known something was up as the nr_dma_* functions all loop until the dma is complete - thus turning the dma into a synchronous memcpy. So if you're expecting true dma behavior you'll have to modify the dma calls. I looked through the NiosII/HAL dma code and it appears to function correctly.

Anyone useing dma's should run a lot of test data through the system under heavy load and check for errors. Setting a SignalTap trigger on the dma's FIFO_FULL is also a good idea.

Ken