--- Quote Start ---
originally posted by rsteiner@Aug 31 2006, 11:13 AM
so what is creating hiccups --- Quote End ---
No hiccups. There are definitely no "hard" errors or like values missing or read twice from a FIFO.
It is simply an increased noise level in the measured values, related to the amount of irregular activity in the NIOS during measurement. Just little, but intolerable.
We know that the same FPGA configuration on exactly the same board can deliver measurement results with half the standard deviation, if the NIOS remained idle in an endless loop and we read the values measured by the logic in the FPGA from outside of the FPGA, using an external CPU.
Unfortunately I cannot explain the actual measurement procedure in more detail. Logic in FPGA and analog circuits outside the FPGA operate tightly connected.
Kolja
Honored Contributor
