Honored Contributor
Honored Contributor<div class='quotetop'>QUOTE </div>
--- Quote Start --- asserts waitrequest during the measurement interval?[/b] --- Quote End --- Yes, that is probably the most promising plan. <div class='quotetop'>QUOTE </div> --- Quote Start --- [if] measurement is triggered by one or more register writes to a peripheral[/b] --- Quote End --- The measurement logic fires at 20 kHz on its own. The NIOS accesses the peripheral regularly but only at 1 kHz rate. Therefore my idea with the "blocking" bridge to SRAM (I wrote "To gate the ACK signal" but what you described is what I actually meant - to assert waitrequest).. SRAM is a peripheral that certainly has to be accessed more often. It wouldn't stop the NIOS executing from cache or onchip memory, but maybe it is already sufficient for us to reduce the communication with external components Maybe the bridge could be moved even nearer to the CPU, between instruction master of core and ALL other slaves? I can't image what side effects that would have... The software is based on embOS. If there was a real IDLE thread, it could continously access the peripheral and block when necessary, but actually we utilize the idle time for low priority data processing. Kolja
