How the avalon mm slave "address alignment" works?

Since you are using the direct macros increment your address by 4 bytes since your slave port is 32-bits wide. So your addresses are: 0x0, 0x4, 0x8, 0xC, etc...

My other recommendation is to include byteenables for your slave port. I normally ignore byte enables on reads if there are no side effects and just use them to register the individual byte lanes coming in. This will make your component more portable to other masters that may use a different data width.

Last but not least make sure you declare your slave port to have 1 cycle of read latency since your read data is registered. Also from a coding perspective I recommend separating the register reads and writes. So have a process for registering the write data, and have another process to register the readdata. Normally I stick to one process per write register since it makes things much easier for making small changes and optimizations. If you want to see an example go ahead and send me a message with your email address and I can forward a component a threw together yesterday that should show this in the HDL.