How the avalon mm slave "address alignment" works?

did u already solved that problem ???

i m just trying to read from my own HDL but i dunno exactly how to use the adress

i got more than 1 parameter where i would like to read/write from/to

i m using the IORD_32DIRECT and IOWR_32DIRECT

but the controll over the address don t work dunno why -.-

sometimes it makes one thing sometimes not.

at the moment i can read from RGB_ADDR but nothing else

and i can write to GRAY and THREST but not to SCREENSHOT -.-

before i had played a bit on the addresses i could set SCREENSHOT but couldn t read or write anything else ...

HELP MEEEEE plz

heres an example:

NIOS II CODE:

#define RGB_ADDR (0x01)# define SCREENSHOT (0x02)# define GRAY       (0x03)# define THRESH   (0x04)# define READOBJEKTX (0x08)# define READOBJEKTY (0x05)# define STARTFOUND (0x06)# define START (0x07)
IOWR_32DIRECT(PICREADANDFIND_0_BASE,SCREENSHOT,0x00000001); 
IOWR_32DIRECT(PICREADANDFIND_0_BASE,GRAY,0x00000001); 
IOWR_32DIRECT(PICREADANDFIND_0_BASE,THRESH,0x00000001); 
start_found=IORD_32DIRECT(PICREADANDFIND_0_BASE,STARTFOUND);
I_XYBILD = IORD_32DIRECT(PICREADANDFIND_0_BASE,RGB_ADDR);

and the Code in Verilog:

module(
        MYADDR,
        MYWRITEDATA,
        MYREADDATA,
        MYWRITE,
        MYREAD
);
input         MYADDR;
input         MYWRITEDATA;
input             MYWRITE;
input             MYREAD;
output    reg      MYREADDATA;
parameter    RGB_ADDR = 8'h01;
parameter SCREENSHOT = 8'h02;
parameter GRAY          = 8'h03;
parameter THRESH      = 8'h04;
parameter READOBJEKTY = 8'h05;
parameter STARTFOUND = 8'h06;
parameter START = 8'h07;
parameter READOBJEKTX = 8'h08;
always@ (posedge CLK50)
begin : AVALON_INTERFACE
    begin
        if(MYWRITE == 1'b1)
        begin
            case(MYADDR)
            SCREENSHOT : screenshotreg <= MYWRITEDATA; 
            STARTFOUND:    getStart <= MYWRITEDATA;
            GRAY: Grayreg <= MYWRITEDATA;
            THRESH:    Threshreg <= MYWRITEDATA;
            default:;
            endcase
        end
        else if((MYREAD == 1'b1) )
        begin
            case(MYADDR)    
            RGB_ADDR: 
            begin
                MYREADDATA <= {xstart}; 
            end
            READOBJEKTX:
            begin
                MYREADDATA <= {xstart};                 
            end
            READOBJEKTY:
            begin
                MYREADDATA <= {32'hFFF11FFF};                   
                 screenshotreg <= ~screenshotreg;
            end
            STARTFOUND:
            begin
                MYREADDATA <={31'h00,set_start};                
            end
            default: MYREADDATA <= 32'hFFFAAFFF;
            endcase
        end
endmodule