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Altera_Forum
Honored Contributor
14 years agoIt's basically a two step boot process. In a first step, the FPGA configuration is loaded from EPCS. This also includes initalized internal FPGA RAM (or "ROM"). Configuration load is common to all FPGA applications, with or without soft processor and starts always from EPCS address 0.
FPGA applications involving a soft processor have usually stored the processor code and initilized data in the EPCS memory. It's loaded to SRAM in a second boot step under control of the NIOS II IP.