HELP:how to remove these timing critical warning

first thanks for your help.

yes I place a pipeline bridge between cpu and jtag. as :

cpu <----->pipeline bridge <---->[jtag uart,sysid,timer,..]

but these critical warning are for the TSE. so it is a little complicated

and difficult to me.

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Look for the top failing paths report in Timequest to determine where you need to add more pipelining.

A typical path that needs a pipeline bridge is the one between the Nios CPU masters (data and instruction) and the CPU's JTAG debug slave interface.

Going over 100MHz on a Nios II system on a Cyclone FPGA is possible, but requires some patience...

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