have warning component is not supported ?

Today I made 2 8bit registers one is writedata and second is readdata conected them to Nios II core as custom made component and tried in nios IDE simple C code which writes to register1 and then reads this value from register 2 I Run debugger (ISS) and got this traditonal Warning and when step through code I couldn't read this second register value as in preveous examples

(inQuartus waveform simulator I simulated Avalon slave signals (readdata and writedata) all was working).

I have read all manuals about Nios II processor in Alteras webpage and also all availible Quartus manuals (more than one time) and there are not discribed sutch situations! all these Examples that are in Nios IDE install directory are too complex to me becose i am beginner in C language (previously code in Assembler)

What is wrong with this bebugger or code ??

C code.

int main()
{
  int i= 0xA8;
  int F;
  IOWR_TLED_PIO_WRITEDATA(TLED_PIO_0_BASE, i);
  F = IORD_TLED_PIO_READDATA(TLED_PIO_0_BASE);
  
}

here is New heder file.

#ifndef __TLED_PIO_REGS_H__# define __TLED_PIO_REGS_H__
# include <io.h>
# define IORD_TLED_PIO_WRITEDATA(base)             IORD(base, 0) # define IOWR_TLED_PIO_WRITEDATA(base, data)       IOWR(base, 0, data)
# define IORD_TLED_PIO_READDATA(base)             IORD(base, 1) # define IOWR_TLED_PIO_READDATA(base, data)       IOWR(base, 1, data)
# endif /* __TLED_PIO_REGS_H__ */

and here is VHDL.

library altera;
use altera.altera_europa_support_lib.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--  Entity Declaration
ENTITY T_pio IS
    -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
    PORT
    (
  chipselect : IN STD_LOGIC;
  clk : IN STD_LOGIC;
  reset_n : IN STD_LOGIC;
  write_n : IN STD_LOGIC;
  writedata : IN STD_LOGIC_VECTOR(7 downto 0);
  address : IN STD_LOGIC_VECTOR(1 downto 0);
  read_n : IN STD_LOGIC;
  readdata : OUT STD_LOGIC_VECTOR(7 downto 0)
    );
    -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
    
END T_pio;
--  Architecture Body
ARCHITECTURE T_pio_architecture OF T_pio IS
   signal clk_en :  STD_LOGIC;
         signal data_out :  STD_LOGIC_VECTOR (7 DOWNTO 0);
   signal data_in :  STD_LOGIC_VECTOR (7 DOWNTO 0);
  signal data_in_out :  STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
    
  clk_en <= std_logic&#39;(&#39;1&#39;);
  --s1, which is an e_avalon_slave
  process (clk, reset_n)
  begin
    if reset_n = &#39;0&#39; then
      data_out <= std_logic_vector&#39;("00000000");
    elsif clk&#39;event and clk = &#39;1&#39; then
      if std_logic&#39;(((chipselect AND NOT write_n) AND to_std_logic((((std_logic_vector&#39;("00000000000000000000000000000000") & (address)) = std_logic_vector&#39;("00000000000000000000000000000000")))))) = &#39;1&#39; then 
        data_out <= writedata(7 DOWNTO 0);
      end if;
    end if;
  end process;
  --s1, which is an e_avalon_slave
  process (clk, reset_n)
  begin
    if reset_n = &#39;0&#39; then
      data_in_out <= std_logic_vector&#39;("00000000");
    elsif clk&#39;event and clk = &#39;1&#39; then
      if std_logic&#39;(((chipselect AND NOT read_n) AND to_std_logic((((std_logic_vector&#39;("00000000000000000000000000000000") & (address)) = std_logic_vector&#39;("00000000000000000000000000000010")))))) = &#39;1&#39; then 
         data_in_out<= data_out(7 DOWNTO 0);
      end if;
    end if;
  end process;
readdata <=data_in_out;
END T_pio_architecture;