"FIFO Interface" component support

--- Quote Start ---

originally posted by kenland@Aug 3 2004, 10:16 PM

that&#39;s ok, i fixed the name length myself. (with right-click->rename in sopc builder http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/rolleyes.gif )

--- Quote End ---

Oh, you meant the component name, not the port names. Gah, I need to find what PTF thing I left out.

The SOPC tutorial pretty much tells everyone that they should rename the components after creating them. I&#39;m wondering why they don&#39;t just put you right into rename mode after you add a component...

--- Quote Start ---

originally posted by kenland+aug 3 2004, 10:16 pm--><div class='quotetop'>quote (kenland @ aug 3 2004, 10:16 pm)</div>

--- quote start ---

yeah, my system has 6msps 10bit/sample adc. i&#39;ll bet that&#39;s is very common to have a need to stream data into a nios for processing. that&#39;s why i was so surprised altera didn&#39;t have a better canned solution or at least an example.[/b]

--- quote end ---

seeing how a super-simple fifo interface like the one you pointed out would be a great example of how to use iul for purposes other than custom component creation... yeah, me, too. ^_-

--- quote start ---

originally posted by kenland@aug 3 2004, 10:16 pm

i&#39;m the master of dummy loads. that&#39;s about all i&#39;ve learned to do. the real stuff i have to rely on you hw types.

--- quote end ---

i&#39;m not much of a type of anything. i&#39;ve done everything from pcb layout to board assembly to dsp to object-oriented design, so the whole hw guys vs. sw guys thing looks pretty silly to me. i&#39;m a big believer in cross-training.

<!--quotebegin-kenland@Aug 3 2004, 10:16 PM

but i think an example that would excercise your port would be a great addition to get people up and running quickly. just because i&#39;ve wasted a few months attempting this doesn&#39;t mean others should have to. http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/smile.gif

--- Quote End ---

The thing is, there&#39;s lots of things you can do to exercise a FIFO port; most of them are pretty trivial to implement. The simplest thing is, of course, create a FIFO and two FIFO Interfaces, one read and one write; hook them up and beat on them.

I&#39;ll be testing things in my environs, but it won&#39;t be exhaustive; hence, the 0.1 version number. I have looked at the generated Verilog, and it looks right, so I&#39;m pretty confident.

But if you have a better idea, or if there&#39;s something obvious I&#39;m missing, please say so.