"FIFO Interface" component support

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originally posted by kenland@Aug 3 2004, 12:35 PM

well i built a system with your fifo. one request is that the port names be shortened, they caused my sopc block to grow in width and break all of my connections.

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Man, the way they name ports (maybe I should post a patch to remove the word "the" everywhere?), I don't see how I'd have any reasonable control over component width. So will omitting the "fifo_" prefix do it for you? Anyone else think it should stay?

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originally posted by kenland@Aug 3 2004, 12:35 PM

i'd like to make a dummy data generator that you give it a data rate and it spits data into your fifo port at that rate. it would be great for testing and verification.

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Sounds good. With or without an actual FIFO being involved? If a FIFO isn't involved, the timing might not be right. The real trick is going to be generating the dummy data.

Forgot to mention... one of the reasons I made this component is because I have a parallel ADC in my system. So I'll need the CPU to configure the ADC, then turn the ADC on and DMA its data through to the FIFO. Also, the CPU needs to write to the FIFO whether or not the ADC is streaming to it (I have flag bits in the data words which allow the streams to get mixed together). Imagine what I'd have to write if I didn't have DMA or the switched fabric/multi-master bus...