"FIFO Interface" component support

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originally posted by kenland+aug 2 2004, 04:48 pm--><div class='quotetop'>quote (kenland @ aug 2 2004, 04:48 pm)</div>

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i haven&#39;t installed your ip yet, but after reading your post i had the silly question of how is your component better than just using a lpm_fifo?

i&#39;m not saying it isn&#39;t, i&#39;m just wanting to learn. i hooked up an lpm_fifo with iul and irq on almost_full, and want to know what that approach lacks. it seemed to work pretty well.[/b]

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hahaha... now that you mention it, an iul instance would cover about half the cases that my fifo interface does; that&#39;s probably why nobody else did this yet. i didn&#39;t think of the flag-to-interrupt connection because my design doesn&#39;t use interrupts. you still have to instantiate an lpm_fifo or somesuch with mine; i take it i didn&#39;t make that clear enough in the docs?

as for what&#39;s different, here&#39;s what i could think of:

[list][*]streaming mode should benefit if you&#39;re reading from a legacy-mode fifo, since iul doesn&#39;t do latency.

[*]used words/free words registers and thresholds.

[*]end-of-packet detection.

[*]can read and/or interrupt on more than one flag, and can change interrupt masks at runtime.

[*]one peripheral instead of two or three.

[*]can block master when writing to full fifo or reading empty fifo.

[*]at some point, i&#39;ll have a character driver for it, so it can work like a uart for interprocessor communication.

[*]on a dual-clock fifo, you don&#39;t have almost-full or almost-empty.

[*]it&#39;s all prefab; you don&#39;t have to recheck the timing every time.

[/list]so basically, you could do almost everything that fifo interface does with an iul, a couple pios (one for flags and one for usedw[]), and a bunch of external logic. it would just be more work.

personally, i&#39;m not a big fan of iul; it took me quite a bit of searching to find the difference between avalon register slave and avalon memory slave; there&#39;s a cool interface for defining ports, but no way to define parameters passed to the top-level entity; and there&#39;s no way to define more than one port (e.g. one iul with both master and slave ports).

<!--quotebegin-kenland@Aug 2 2004, 04:48 PM

i&#39;ve had trouble achieving 100% on both streaming dma and driving a master port. would your component be a good buffer for either of these to avoid that 1% loss?

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I can&#39;t say without knowing what the 1% loss is from...