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Altera_Forum
Honored Contributor
16 years agoF.Y.I u-boot and TSE/SGDMA in Q9.1
This is just F.Y.I I spent quite a time for debugging and noticed that the u-boot TSE driver with M88E1111 combination may not work properly in Q9.1 compiled H/W design. We compiled the 3C120(...
Altera_Forum
Honored Contributor
15 years agoHi
I have had a similar problem working in 10.1. Found the sollution to be the RUN bit in the DMA controller control register (the receive SGDMA). it seems as though it is required to first clear the bit and then re-enable it when updating the descriptor memory to process the next message. In u-boot\drivers\net\altera_tse.c I had to modify alt_sgdma_do_async_transfer to the following (note that this is the async and not the sync function)
static int alt_sgdma_do_async_transfer(volatile struct alt_sgdma_registers *dev,
volatile struct alt_sgdma_descriptor *desc)
{
unsigned int status;
int counter = 0;
/* Wait for any pending transfers to complete */
alt_sgdma_print_desc(desc);
status = dev->status;
counter = 0;
while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) {
if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
break;
}
if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
debug("Timeout waiting sgdma in do async!\n");
/*
* Clear any (previous) status register information
* that might occlude our error checking later.
*/
/* Get & clear status register contents */
dev->status = 0xFF;
debug("rx sgdma status = 0x%x\n", status);
dev->control &= ~ALT_SGDMA_CONTROL_RUN_MSK; //clear run bit
/* Point the controller at the descriptor */
dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF;
/*
* Set up SGDMA controller to:
* - Disable interrupt generation
* - Run once a valid descriptor is written to controller
* - Stop on an error with any particular descriptor
*/
dev->control = (ALT_SGDMA_CONTROL_RUN_MSK |
ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK);
/* we really should check if the transfer completes properly */
return 0;
}
I can now tftp and ping from u-boot. Regards, Antonie