Ethernet on 3C120

Hi,

I am also working on a 3C120 Development board ethernet design on a Nios2 running uClinux.

I am so close to a solution but run into problems with both the "tripple speed ethernet" and the "triple speed ethernet" options.

With the Tripple Speed Ethernet option (the one that is said to work) - I get a build error at atse.c line 1485, saying it cant find the "get_stats" field in the Network Device descriptor. Does anyone know what would cause this?

With the Triple Speed Ethernet option ...the design builds but when I download the terminal reports that the kernel has successfully uncompressed and starting but it just hangs there. If I disable the Triple Speed Mac - the sash shell goes through to prompt. Does anyone know what might cause this sort of effect?

I have been very careful trying to emulate the various example designs for use of the tse_mac in hardware ... and believe I have a good design, except for one question that I see different from working examples to your pictures in this forum. There is a 180 degree phase shift on the 125MHz clocks in the designs here ... BUT when I reverse engineered the verilog of the uCos based webserver design I did not get this hardware picture at all. What I get is a comment that the clock is 180 degrees BUT when you actually open the pll its 90 on the gtx clock and 90 on the rx clock.

The 125MHz rxclk pin is connected to a source synchronous pll which regenerates the 125MHz signal with a 90 degree phase shift and passes it to the SOPC tse_mac rx clock input

Another PLL phase locks up the system clock to produce two outputs ... a 125MHz tx clock to the tse mac at 0 degrees and ther gtx clock at 90 degrees...???

Also there is an interesting technique on the 125MHz gtx clock output pin where the physical clock is reconstructed with a DDIO - where the clock selects hardwired Positive and negative levels on positive and negative clock edges respectively. I am thinking that this probably allows propogation deelay skew to be controlled more easily in the assignment editor... which may be the reason why there are difficulties in either Rx and Tx in these designs? I dont know...just thinking out loud - it seems a little odd.

Regardless ... the setup is supposed to work for the example (I have not tried it myself - bit probably should)... which makes me think something different here with respect to what you may have?

If anyone can help it would be much appreciated.

If anyone out there is struggling with this (like me) and wants to collaborate in with text text ... please let me know ... maybe we can help each other?