Dual Nios cores - but a catch - one's behind the "black box" wall

You can certainly compile and link nios code outside of the IDE and without all the headers generated by the sopc builder (etc).

I'd much rather have a memory map (etc) specified, and the C headers and fpga image both built to match the specification.

JTAG download and debug are a different issue.

I presume you want to download the fpga itself from on-board memory - or, at least, not over JTAG from quartus. Which makes a lot of sense anywhere where the hardware and software are written by different people (even if they are only a few desks apart).

We download nios code (and do any debugging) using the PCIe slave interface. Not having breakpoints or source level debug isn't that much of a hardship - you can't really breakpoint real-time (or comms protocol) code since the rest of teh world doesn't stop.