Forum Discussion
Altera_Forum
Honored Contributor
15 years agoFirst off, I'd try getting the IDE/SBT for Eclipse out of the way.... From a "Nios II Command Shell" (or a properly configured shell on Linux) change directories to where your ELF file is stored and type the following command:
nios2-download -g <your ELF.elf> && nios2-terminal and report what you see back here. If this command doesn't appear to work, please also try typing: jtagconfig -n and report the results here, as well. This will help to determine whether the issue you're seeing is GUI/Eclipse related, JTAG chain related, hardware/FPGA design related or...something else. Cheers, -- slacker- Amruth4 years ago
New Contributor
Hii
I am also facing the same error for simple soc design on stratix 10 MX FPGA. I checked the connections, configurations and tried running through nios II command shell. But getting the error
Using cable "Intel Stratix 10 MX FPGA Development Kit [2-1.2]", device 1, instance 0x00
Pausing target processor: not responding
Resetting and trying again: FAILED
Leaving target processor paused
My quarters prime edition is 18.1.2 pro. Can you please help me out.