DMA data transfer when waitrequest presents

Hi, I have connencted user defined module on avalon bus. this component issue waitrequest signal for each data access both in dma mode and normal reg access mode.

When I don't connect waitrequest signal to avalon bus, the dma is issueing the correct number of read signals(I programed it for 4 and it is giving 4) per burst access. And also normal reg read/write happening fine.

When I connect waitrequest signal to avalon bus, the normal reg read/write is happening fine but in dma transfer case, the dma is issueing only one read signal(actually it should give 4 read signals) per burst access.

Connecting waitrequest on avalon bus is compulsory, but I need to use dma.

Please suggest me some solution to do dma transfer, and also please let me know the reason why it is issueing only one read signal.

Thanks a lot for the suggester.

Venkat.