Device drivers under niosII IDE

Thanks to your helpful answers sincerely. But I still have someting unclear with the timing of bus transfer. It's easy to understand the timing is determined by the slave when using "Slave Read or Write Transfer with Peripheral-Controlled Wait States." But when using "Slave Write Transfer with Setup and Hold Time" or "Slave Read Transfer with Fixed Wait States or with Setup Time", how does the master port generate the corresponding timing according to the relevant PTF parameters of Setup_Time & Wait_States, Hold_Time ?