Delayed Interrupt

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It's not easy to help you without knowledge of your system implementation. I can only make a few guesses.

First of all, the delay is in the 2us range. This short time is very difficult to manage in software.

You excluded this delay is due to higher priority interrupts, but common hw processes, like bus arbitration, memory burst accesses or other unpredictable events can lead to a non neglectable delay in this range.

What's you processor system clock frequency? Is Nios the only bus master or do you have dma?

Please also specify where the irq comes from. Is this a PIO interrupt? And how do you read the data being lost?

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What's you processor system clock frequency? 165mhz

Is Nios the only bus master or do you have dma? yes, nios the only bus master i do not have any dma

Please also specify where the irq comes from. Is this a PIO interrupt? yes this is a pio interrupt

And how do you read the data being lost? its visiable on la and at receiver i am not getting data also

At every interrupt I read 2D array ImgBuff[460][640]

do
{
if(edge_capture)
{
//Clear generated interrupt
edge_capture = 0;
IOWR_ALTERA_AVALON_PIO_DATA(TEMP_OUT_BASE,1); //(shown on LA)
IOWR_ALTERA_AVALON_PIO_DATA(DATA_BASE,ImgBuff);//(shown on LA)
Count++;
}
	if(Count == PktSize)	//check end of packet-data
	{
	Count = 0;			//Point to Start of packet data
	LPktCount++;    		//Increment packet Count
	}
IOWR_ALTERA_AVALON_PIO_DATA(TEMP_OUT_BASE,0); //(shown on LA)
}while(LPktCount != (PktCount+1));