Honored Contributor
Honored Contributori have a custom core, a controller, two separate data memories (mema and memb) and two nios ii processors. custom core writes data to mema and nios processors must read data from mema and after processing these data, they have to write the result to memb. now, custom core must read data from memb. so, just custom core will write to mema and just nios processors write data to memb. controller will specify the read and writes for nios processors and custom core. i don’t know how i can connect nios processors and custom core to mema and memb. do i connect the mema and memb to nios pio? how nios processors can read from and write to these memories? how the controller can pass the addresses to nios processors? please be aware that possibly there is write conflict to memb, so do i have to use mutex? please help me, i’m completely confused.
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--- Quote End --- The easiest way would be to have your custom cores access the memory using Avalon-MM master ports. You may just create a bridge that converts your custom core transfers over to the system interconnect fabric. Then you can just use the on-chip memory component that comes with SOPC Builder. The arbitration between your custom cores and two Nios II processors will be created automatically by SOPC Builder. If there is a possibility of your custom cores and Nios II processors communicating with the memory at the same time then you should use a mutex. In SOPC Builder there is a mutex component you can use to "lock" the memory. To learn more I recommend reading some of the topics on these two pages: http://www.altera.com/literature/lit-nio2.jsp (http://www.altera.com/literature/lit-nio2.jsp) http://www.altera.com/literature/quartus2/lit-qts-sopc.jsp (http://www.altera.com/literature/quartus2/lit-qts-sopc.jsp)
