Creating Memory device for Nios II processor

Hi Martin,

I think Socrates is somehow misleading you. The point is not DMA.

DMA is simply a method used to transfer data from one slave memory device to another.

Any slave device (MM or streaming) can be used both with DMA and normal memory access; the difference is that DMA exploits an external master engine (independent from cpu) to transfer data from one location to another, while in usual memory transfers the bus master is the cpu itself which performs the same operations.

Then, IORD/IOWR can be also performed by equivalent pointer operations.

If you need to bypass cache you simply need to raise address bit 32.

Example:

IOWR(MM_BASE,offset,data);

is equivalent to:

int * addr = MM_BASE+offset

*addr = data;

data = IORD(MM_BASE, offset);

is equivalent to :

data = *addr;

data = *(addr | 0x80000000); // the same as above, with cache bypass

Regarding the other questions:

- yes, you can have a read only interface.

- support for burst tranfers is not mandatory; I'm not sure but I believe you specify the burst support feature in the tcl script of the sopc/qsys component. Pipeline is usually managed by a specific adapter component inserted between the Avalon bus and the MM slave.

Regards