Compact Flash HW & SW Examples

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originally posted by davew+jun 20 2006, 04:14 pm--><div class='quotetop'>quote (davew @ jun 20 2006, 04:14 pm)</div>

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<!--quotebegin-viethoang@Jun 13 2006, 05:47 PM

i did as your instructions, but when i ran sopc builder to regenerate, it issued an error:

ERROR: in F:/altera/mywork/CF/cf_examples_for_niosforum/std_cf_2c35/std_2C35.ptf, can&#39;t read Clock_Source setting for ddr_sdram instance of ddr_sdram_component v3.2.0.[/b]

How can I fix this bug?

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I had a similar problem and I&#39;m hoping someone out there can provide some guidance on this one.

Thanks,

Dave

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=16274)</div>

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The new ddr core 3.4.0 needs a new resync clock.

You may try another method, copy the project,

altera/kits/nios2_60/examples/verilog/niosII_cycloneII_2c35/standard

add cf component, wire it in top level to cf socket for cf drive or a 20x2 pin header for IDE HDD/DVD writer .

assign the pins. and regenerate to build sof.