Hi,
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But how did you handle cache synchronization and the inter-CPU atomic operations that are necessary to do the Mutex API and the multiple Kernel-internal synchronization issues ?
(I understand that this is close to impossible without modifying the CPU design.)
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At first, I removed the normal data cache from the Nios2/f core (select the data cache <none> option in the SOPC builder) and added my original 1st (write-through) data cache. The cache synchronization method is the same one that is used in the clone's case. For atomic memory operations, I implemented the 'swap' that is controlled as a custom instruction. Unfortunately, we can't use cache non-cache information outside of Nios2 core, so I changed the kernel memory mapping like
0xc0000000-0xcfffffff : cacheable
0xd0000000-0xdfffffff : non-cacheable
0xe0000000-0xefffffff : cacheable
0xf0000000-0xffffffff : non-cacheable
.
Kazu