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Altera_Forum
Honored Contributor
Honored ContributorCan I upload Nios2 SMP system?
Hi, guys & Altera corp. I'm now making a Nios2 SMP system for my research purpose. It's still a little bit buggy and slow, but I succeeded to boot Linux kernel and execute bash.
Linux ...
Altera_ForumHonored Contributor
Honored ContributorHi,
--- Quote Start --- My point about readra/readrb is that the logic that handles the pipeline stall doesn't really want to look that far into the instruction decode. --- Quote End --- Maybe, Altera uses embedded memories for the Nios's register files, and sets those in the same clock phase of the 'Decode Stage'. To read the contents of the embedded memories, it takes one clock, so the RA & RB field data must be sent directly from the 'Fetch Stage' to the register file. The contents of the register file are always discharged to the following stage even when those are not used. But to avoid the 'RAW' hazard, the 'Decode Stage' must decide whether the RA and RB are really used or not. I don't know whether Altera uses readra and readrb bits for this purpose or not, because the 'R0' register can be used instead of those. Kazu
