Honored Contributor
Honored ContributorDSL means don't hook up the tightly coupled data master and the regular data master up to each port of a dual-port on-chip memory. If you did that you would have two data paths into the same memory which will cause problems at the linking stage.
Assigning the ports to different addresses would remove this but then it opens up a new case of worms since you'll have aliased memory if you did that. There is no reason to have both types of data masters connected to a single memory so just don't do it. Typically when people dual port a tightly coupled memory it is to put instructions into it when you connect the 2nd port to a tightly coupled instruction master. The other common usage is to share data without having to worry about cache coherency (other processors or DMAs in your system can access the TCM without you needing to worry about the L1 data cache coherency since TCM accesses always bypass the cache).
