Burst transfer using the NiosII

DSL is correct, the only time either Nios II master performs a burst larger than 1 is when bursting is enabled and a cache line is being read or written out (assuming the data cache line size > 4 bytes).

If you are using Altmemphy (HPII) or Uniphy you no longer need to use bursting to get good efficiency out of them. Those memory controllers support transaction merging so when the controller receives sequential or short burst accesses it attempts to merge them into a single off-chip burst. For example to get good efficiency out of Nios II this is what I would do:

1) Set the SDRAM controller local burst size to 1

2) Use 32B/line Nios II caches with bursting disabled

3) Crank the arbitration share of the instruction and data masters connected to SDRAM to 8

The arbitration share of 8 will make sure the cache line movements don't pingpong back and forth for access to the SDRAM (trying to keep each master accessing memory for 8 back to back accesses which matches the line size). So if you did the same for your hardware accelerator you can eliminate some burst complexity from your system.