Burst transfer using the NiosII

I believe the only way the nios can do burst memory cycles is when doing cache line fill/write.

Normal uncached avalon memory cycles are always done synchronously - ie the nios cpu stalls for the entire avalon cycle (the 'result delay' for reads happens after this stall).

The 'tightly coupled data' interface isn't public - so you can't use that to interface to custome logic.

A couple of options for avoiding the avalon bus stalls:

1) use a tightly coupled memory block and get your logic to transfer to from the dual port of that memory

2) access from within the custom instruction logic - needs a little lateral thought