Honored Contributor
Honored ContributorI will try it again after changing the reset vector. The elf2flash does output one warning and the it about the reset vectors not matching.
I'm a bit confused on where the firmware(NIOS code) is loaded. This dev board has a MAX V device that is attached to the FPGA and the flash and manages loading the FPGA. In the previous post I included an image of the CFI flash map. My intent is to load my hardware code into the "User Hardware 1" block and then to load my software into the "User Software" block. Then at power up, the Max V configures the FPGA based on a dip switch setting. Only one part of this process is working for me. It seems that the "User Hardware 1" is loaded at power up but I can't say what has happened with the "User Software". I can only say that the NIOS processor is not running. I'm not sure if the base of 0x0 is correct of if it should have been at another location.
