Bad start-byte

Hello Terry,

I have had many problems with the flash programmer (which are not solved, but I know why now :-) ) and I think that a possible cause to your problem is the frequency of your design. What speed do you run the FPGA ? I had problems when my design did not run around 50 MHz (40 failed, but 60 too....). In my case the error changed regularly (bad start byte, bad JTAG frame or no communication at all). To solve this I had to add a PLL at the clock input of the FPGA, and a delay on the reset pin of the Nios2 to allow the PLL to stabilize (but not too long because it caused problems too, probably a time out...). I used approximately the same delay as the one used in the default design (from altera) of my cyclone dev board (the cout of an 11-bit counter worked the best for me, when my input clock was 20Mhz and that I tried to boost it up to 50 MHz with a PLL).

I hope this helps

Pod