The error we got was "Error (275046): Illegal name "slave_mm_io_datain_119" -- pin name already exists" we get this for a number of other pins. Reasoning being that the bit number is just appended to the register number, therefore confusing register 1 bit 19 with register 11 bit 9. By going into the tcl and changing "user_datain_10" to "user_datain_a" and so on this resolved itself.
We're using schematic capture with this just to quickly test functionality, with our custom logic going to be writen in verilog. Attached are the original tcl and verilog files and our schmatic layout.
If we now write to the registers in one order we expect to read back with the numbers reversed, due to the wiring.
However what we get is a 0's from register 0 to 11 and then a block of 4 of one number then 0's the rest of the way down. we sent 2 numbers and alternated them.
any suggestions?