Avalon-MM Master reading

No, I use SDRAM. However if I remove that watchdog counter, the reading master gets stuck in the state after read signal assertion, waiting for readdatavalid to go high. Since readdatavalid never goes high, all the logic after this part stops working. I know I had to simulate the design, but I was too lazy to write a testbench after I came with this workaround.

I've also wasn't able to catch that situation with signaltap, since it occurs very fast, but there were no other logic explanations, since the only check for the current state was checking for readdatavalid to go high.

Now I see readdatavalid to go high in about 7-12 clk cycles after I assert read signal for one cycle.