Avalon bus with 2 Avalon_MM_ Slaves fails to work (works fine with 1...)

The reason why chip select is not recommended is because the fabric already generates qualified read and write signals. It generates a chip select by performing a logical OR of those signals to generate the chip select line. So if you use that to qualify the read and write signals at the slave side it's redundant. Most users omit the chip select of the slave port and use read and write directly and that's Altera's recommendation in the specification. Qsys is not generating a shared bus interconnect, it's a partial crossbar implemented as a NoC. So transactions flow through the fabric and can only arrive at one end point (slave), the only way multiple slaves can be issued transactions at the same time is if there are multiple masters issuing the transactions in the system. That quote from the spec is stating if you include a chip select port then you *must* include read/write ports as well. The second part is saying chipselect is optional and not recommended because the fabric doesn't issue non-qualified transactions to slaves anyway.

I didn't follow the bug, but someone was showing me an issue around a year ago with the chip select polarity in a system. I told them remove the chip select since it makes no sense to use with an Avalon slave in Qsys and the problem went away. I have also seen people try to include a chip select port on their Avalon master interfaces, I have no clue what will happen in those cases but if you are doing that I highly recommend removing it.