Accessing memory in user logic

An alternative view is that the nios2 accesses avalon slave peripherals in much the same way as any 32bit micro. The two low address bits (often called A0 and A1) are converted into 4 byte enable lines, the remaining address lines are use to select the actual device and register (etc).

So if you want to do a byte write, the actual bus write cycle only has 1 of the 4 byte enables asserted.

A single cpu instruction can also only generate 1 (32bit) bus cycle, so you can't do misaligned accesses (ie read a 32bit word from an odd address).

There are a couple of things that complicate matters:

1) Bus width adapters. If you define an avalon slave with only 8 bit data, the system inserts logic to convert the 32bit cycle generated by the nios into four 8bit cycles to your slave. Although useful when connecting narrow memory, for IO it is rather a PITA and it is best to make your avalon slave a 32bit slave by returning 0 for all the high data bits.

I don't know how the 32->8 bit bus adapter works, but the one that converts 64->32 bits (used in the PCIe slave) generates cycles with no byte enables asserted!

2) The nios cpu always asserts all 4 byte enables on reads, and discards the unwanted bytes internally.