Accessing memory in user logic

Thank you!

I think I have sort of got the picture now.

The Avalon address signal actually represents "how many 4bytes are there " rather than just normal address.

eg. ADDR[2:0] mapping into a 8 bits memory-map RAM would not just address my RAM from its BASE to BASE+7 but actually, it means to provide 8 segments of address in which each segment contains 4 bytes. If the data in a register does not have 4 bytes, eg. 2 bytes, the remaining 2 bytes address is reserved to keep the alignment up.

Hence, the actual RAM address would start from BASE to BASE+8*32.

And in this case I can access the SAME register using different addresses

eg. The first register has a data width of 2 bytes and I can access that particular register at any address ranging from BASE+0 to BASE+0xFF, but in the next 2 byes range from 0xFF to 0xFFFF I will simply get nothing. Then after 0xFFFF, I will be accessing the 2nd register and so on.

Please correct me if my understanding is any slightly wrong

Thank you!